Module Leader: Prof. J W Gardner

Co-lecturer: Dr S.T. Davies

Module Information

Scope

This 30 CATS module is one of the third year modules for:

Aims

The course aims to present the principles and techniques of both digital (15 credits) and analogue (15 credits) VLSI design, connecting digital system, logic design, and analogue components with the fundamental device physics, processing techniques and transistor level characteristics of Silicon integrated circuits, both in theortical and practical aspects.

Learning Outcomes

By the end of the module the student should be able to...

• Appreciate the properties of VLSI technology and how they affect logic implementation, optimisation and system design.
• Undestand the role of, and aquire skills in, the use of Computer Aided Design Software for VLSI.
• Use a variety of technologies, design objectives and anaylsis techniques appropriate to VLSI applications.

Syllabus

Digital VLSI: Silicon Processing. CMOS circuits for logic gates. Cell layout styles. Cell composition and structured layout techniques. Transmission gate logic and dynamic memory. Latches. Complex CMOS gates. Dynamic logic. Timing analysis and optimisation. Power dissipation. Subsystem design: adders, parallel and serial multipliers, RAM, datapath and PLA/ROM. Design Exercises to Cover cell layout and composition, switch level simulation and timing analysis, critical path finding and circuit level simulation for timing and power. Example circuits: 16 bit counter and first order digital filter.

Analogue VLSI: Processing and circuit design using: bulk, epi and SOI Bipolar, CMOS and BiCMOS silicon technologies. Future technologies including gallium arsenide. Analogue VLSI components: passive components (resistors, capacitors), power sources (voltage and current), current mirrors, operational and instrumentation amplifier, ADCs and DACs. Case studies for CMOS devices (i.e. circuits and sensors). Design exercise to cover analogue cell layout and composition, modelling and circuit level simulation for voltage output and fequency dependence. Example circuits: current sources, voltage reference, op-amps, current mirrors..

Teaching Methods

This module includes 25 hours of lectures and 30 hours of laboratory sessions.

Required self-study: 243 hours

Assessment

A 30 CATS module: 50% examined via a 3 hour paper

Exam rubric information:

• 4 Compulsory Questions

and 50% assessed consisting of:

• Electronic Submission of Digital Designs (12.5%)

• Digital Design Report (12.5%)

• Electronic Submission of Analogue Designs (12.5%)

• Analogue Design Report (12.5%)

Links to:

Student Resources

Staff Pages

Reading List

Recommended Textbook:

N.H.E. Weste & D. Harris, CMOS VLSI design : a circuits and systems perspective, 3rd ed., London : Pearson/Addison-Wesley, c2005