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Publications

Below you will find a list of my publications and links to download them. Note that they are provided here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders.

You can also view my Google Scholar Citations Profile, DBLP Profile, and ORCID Profile, and my publications on the Warwick repository, WRAP.

Peer-Reviewed Conference Papers

  1. X. Li, A. K. Jain, D. L. Maskell and S. A. Fahmy, “A Time-Multiplexed FPGA Overlay with Linear Interconnect”, to appear in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2018.

  2. S. I. Roberts, S. A. Wright, S. A. Fahmy, S. A. Jarvis, “Metrics for Energy-Aware Software Optimisation”, in Proceedings of ISC High Performance (formerly International Supercomputing Conference), Frankfurt Germany, June 2017, pp. 413–440.

  3. S. Shreejith, A. Ambede, A. P. Vinod, and S. A. Fahmy, “A Power and Time Efficient Radio Architecture for LDACS1 Air-to-Ground Communication”, in Proceedings of the Digital Avionics Systems Conference (DASC), Sacramento, CA, September 2016.

  4. M. Vesper, D. Koch, K. Vipin, and S. A. Fahmy, “JetStream: An Open-Source High-Performance PCI Express 3 Streaming Library for FPGA-to-Host and FPGA-to-FPGA Communication”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 2016.

  5. B. Ronak and S. A. Fahmy, “Improved Resource Sharing for FPGA DSP Blocks”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 2016.

  6. A. K. Jain, D. L. Maskell, and S. A. Fahmy, “Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?”, in Proceedings of the IEEE International Conference on Pervasive, Intelligence and Computing (PICom), Auckland, New Zealand, August 2016, pp. 586–593.

  7. A. K. Jain, D. L. Maskell, and S. A. Fahmy, “DeCO: A DSP Block Based FPGA Accelerator Overlay With Low Overhead Interconnect”, in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Washington, DC, May 2016, pp. 1–8.

  8. A. K. Jain, D. L. Maskell, and S. A. Fahmy, “Throughput Oriented FPGA Overlays Using DSP Blocks”, in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016, pp. 1628–1633.

  9. S. Shreejith, B. Anshuman, and S. A. Fahmy, “Accelerated Artificial Neural Networks on FPGA for Fault Detection in Automotive Systems”, in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016, pp. 37–42.

  10. L. Yang, M. Ikram, S. Gurumani, S. A. Fahmy, D. Chen, and K. Rupnow, “JIT Trace-Based Verification for High-Level Synthesis”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Queenstown, New Zealand, December 2015, pp. 228–231.

  11. B. Ronak and S. A. Fahmy, “Minimising DSP Block Usage Through Multi-Pumping”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Queenstown, New Zealand, December 2015, pp. 184–187.

  12. S. A. Fahmy, K. Vipin, and S. Shreejith, “Virtualized FPGA Accelerators for Efficient Cloud Computing” in Proceedings of the IEEE International Conference on Cloud Computing Technology and Science (CloudCom), Vancouver, Canada, November 2015, pp. 430–435.

  13. K. Vipin and S. A. Fahmy, “Mapping Adaptive Hardware Systems with Partial Reconfiguration Using CoPR for Zynq” in Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Montreal, Canada, June 2015.

  14. S. Shreejith and S. A. Fahmy, “Security Aware Network Controllers for Next Generation Automotive Embedded Systems” in Proceedings of the Design Automation Conference (DAC), San Francisco, CA, June 2015, pp. 39:1–39:6.

  15. P. Mundhenk, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, and S. Chakraborty, “Security Analysis of Automotive Architectures using Probabilistic Model Checking” in Proceedings of the Design Automation Conference (DAC), San Francisco, CA, June 2015, pp. 38:1–38:6.

  16. A. K. Jain, X. Li, S. A. Fahmy, and D. L. Maskell, “Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq”, in Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Boston, MA, June 2015.

  17. A. K. Jain, S. A. Fahmy, and D. L. Maskell, “Efficient Overlay Architecture Based on DSP Blocks”, in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Vancouver, Canada, May 2015, pp. 25–28.

  18. S. Shreejith, B. Banarjee, K. Vipin, and S. A. Fahmy, “Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA”, in Proceedings of the International Conference on Cognitive Radio Oriented Wireless Networks (CROWNCOM), Doha, Qatar, April 2015, pp. 427–437.

  19. P. Mundhenk, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, and S. Chakraborty, “Lightweight Authentication for Secure Automotive Networks”, in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Grenoble, France, March 2015, pp. 285–288.

  20. H. Y. Cheah, S. A. Fahmy, and N. Kapre, “On Data Forwarding in Deeply Pipelined Soft Processors”, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2015, pp. 181–189.

  21. S. Shreejith and S. A. Fahmy, “Zero Latency Encryption with FPGAs for Secure Time-Triggered Automotive Networks”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Shanghai, China, December 2014, pp. 256–259.

  22. H. Y. Cheah, S. A. Fahmy, and N. Kapre “Analysis and Optimization of a Deeply Pipelined FPGA Soft Processor”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Shanghai, China, December 2014, pp. 235–238.

  23. M. Lukasiewycz, S. Shreejith, and S. A. Fahmy, “System Simulation and Optimization using Reconfigurable Hardware”, in Proceedings of the International Symposium on Integrated Circuits (ISIC), Singapore, December 2014, pp. 468–471.

  24. K. Vipin and S. A. Fahmy, “DyRACT: A Partial Reconfiguration Enabled Accelerator and Test Platform”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014.

  25. B. Ronak and S. A. Fahmy, “Efficient Mapping of Mathematical Expressions into DSP Blocks”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014.

  26. K. Vipin, S. Shreejith, S. A. Fahmy, and A. Easwaran, “Mapping Time-Critical Safety-Critical Systems to Hybrid FPGAs” in Proceedings of the IEEE International Conference on Cyber-Physical Systems, Networks, and Applications (CPSNA), Hong Kong, China, August 2014, pp. 31–36.

  27. P. Choi, J. Gao, N. Ramanathan, M. Mao, S. Xu, C. C. Boon, S. A. Fahmy, and L. S. Peh, “A Case for Leveraging 802.11p for Direct Phone-to-Phone Communications”, in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, CA, August 2014, pp. 207–212.

  28. T. H. Pham, I. V. McLoughlin, and S. A. Fahmy, “Shaping Spectral Leakage for IEEE 802.11p Vehicular Communications”, in Proceedings of the IEEE Vehicular Technology Conference (VTC Spring), Seoul, Korea, May 2014.

  29. K. Vipin and S. A. Fahmy, “Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq”, in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014, pp. 202–205.

  30. S. Xu, S. A. Fahmy, and I. V. McLoughlin, “Square-Rich Fixed Point Polynomial Evaluation on FPGAs”, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2014, pp. 99–108.

  31. S. Shreejith, S. A. Fahmy, and M. Lukasiewycz, “Accelerating Validation of Time-Triggered Automotive Systems on FPGAs”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Kyoto, Japan, December 2013, pp. 4–11.

  32. K. Vipin, S. Shreejith, D. Gunasekara, S. A. Fahmy, and N. Kapre, “System-Level FPGA Device Driver with High-Level Synthesis Support”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Kyoto, Japan, December 2013, pp. 128–135.

  33. K. R. Shetti, S. A. Fahmy, and T. Bretschneider, “Optimization of the HEFT algorithm for a CPU-GPU environment”, in Proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies, Taipei, Taiwan, December 2013, pp. 212–218.

  34. F. Brosser, H. Y. Cheah, and S. A. Fahmy, “Iterative Floating Point Computation Using FPGA DSP Blocks”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, September 2013.

  35. M. Lukasiewycz, S. Steinhorst, S. Andalam, F. Sagstetter, P. Waszecki, W. Chang, M. Kauer, P. Mundhenk, S. Shreejith, S. A. Fahmy, S. Chakraborty, “System Architecture and Software Design for Electric Vehicles”, in Proceedings of the Design Automation Conference (DAC), Austin, TX, June 2013, Article 95.

  36. K. D. Pham, A. K. Jain, J. Cui, S. A. Fahmy, and D. L. Maskell, “Microkernel Hypervisor for a Hybrid ARM-FPGA Platform”, in Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington, DC, June 2013, pp. 219–226.

  37. K. Vipin and S. A. Fahmy, “Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems”, in Proceedings of the Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW) – Reconfigurable Architectures Workshop (RAW), Boston, MA, May 2013, pp. 172–181.

  38. S. Xu, S. A. Fahmy, and I. V. McLoughlin, “Efficient Large Integer Squarers on FPGA”, in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Seattle, WA, April 2013, pp. 198–201.

  39. S. Shreejith, K. Vipin, S. A. Fahmy, and M. Lukasiewycz, “An Approach for Redundancy in FlexRay Networks Using FPGA Partial Reconfiguration”, in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Grenoble, France, March 2013, pp. 721–724.

  40. H. Y. Cheah, S. A. Fahmy, and D. L. Maskell, “iDEA: A DSP Block Based FPGA Soft Processor”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Seoul, Korea, December 2012, pp. 151–158. Best Paper Award Winner

  41. K. Vipin and S. A. Fahmy, “A High Speed Open Source Controller for FPGA Partial Reconfiguration”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Seoul, Korea, December 2012, pp. 61–66.

  42. B. Ronak and S. A. Fahmy, “Evaluating the Efficiency of DSP Block Synthesis Inference from Flow Graphs”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 2012, pp. 727–730.

  43. K. Vipin and S. A. Fahmy, “Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration”, in Reconfigurable Computing: Architectures, Tools and Applications – Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC), Hong Kong, March 2012, pp. 13–25.

  44. S. Chakraborty, M. Lukasiewycz, C. Buckl, S. A. Fahmy, N. Chang, S. Park, Y.Kim, P. Leteinturier, and H. Adlkofer, “Embedded Systems and Software Challenges in Electric Vehicles”, in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2012, pp. 424–429.

  45. H. Y. Cheah, S. A. Fahmy, D. L. Maskell, and C. Kulkarni “A Lean FPGA Soft Processor Built Using a DSP Block”, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2012, pp. 237–240.

  46. K. Vipin and S. A. Fahmy, “Efficient Region Allocation for Adaptive Partial Reconfiguration”, in Proceedings of the International Conference on Field Programmable Technology (FPT), New Delhi, India, December 2011.

  47. S. A. Fahmy, “Histogram-Based Probability Density Function Estimation on FPGAs”, in Proceedings of the International Conference on Field Programmable Technology (FPT), Beijing, China, December 2010, pp. 449–453.

  48. P. D. Sutton, J. Lotze, H. Lahlou, B. Özgül, S. A.Fahmy, K. E. Nolan, J. Noguera, and L. E.Doyle, “Multi-Platform Demonstrations using the Iris Architecture for Cognitive Radio Network Testbeds”, in Proceedings of the International Conference on Cognitive Radio Oriented Wireless Networks and Communications (CrownCom), Cannes, France, June 2010.

  49. L. E. Doyle, P. D. Sutton, K. E. Nolan, J. Lotze, B. Özgül, T. W. Rondeau, S. A. Fahmy, H. Lahlou, and L. A. Dasilva, “Experiences from the Iris Testbed in Dynamic Spectrum Access and Cognitive Radio Experimentation”, in Proceedings of the IEEE Symposia on New Frontiers in Dynamic Spectrum Access Networks (DySPAN), Singapore, April 2010.

  50. S. A. Fahmy and L. E. Doyle, “Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing”, in Reconfigurable Computing: Architectures, Tools and Applications – Proceedings of the International Symposium on Applied Reconfigurable Computing (ARC), Bangkok, Thailand, March 2010, pp. 343–350.

  51. J. Lotze, S. A. Fahmy, J. Noguera, B. Ozgül, and L. Doyle, “Spectrum Sensing on LTE Femtocells for GSM Spectrum Re-Farming Using Xilinx FPGAs”, in Proceedings of the Software-Defined Radio Forum Technical Conference (SDR Forum), Washington, DC, December 2009.

  52. J. Lotze, S. A. Fahmy, J. Noguera, B. Ozgül, L. Doyle, and R. Esser, “Development Framework for Implementing FPGA-Based Cognitive Network Nodes”, in Proceedings of the IEEE Global Communications Conference (GLOBECOM), Honolulu, Hawaii, December 2009.

  53. S. A. Fahmy, J. Lotze, J. Noguera, L. Doyle, and R. Esser, “Generic Software Framework for Adaptive Systems on FPGAs”, in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Napa, CA, April 2009, pp. 55–62.

  54. S. A. Fahmy, “Generalised Parallel Bilinear Interpolation Architecture for Vision Systems”, in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, December 2008, pp. 331–336.

  55. J. Lotze, S. A. Fahmy, J. Noguera, L. Doyle, and R. Esser, “An FPGA-based Cognitive Radio Framework”, in Proceedings of the IET Irish Signals and Systems Conference (ISSC), Galway, Ireland, June 2008, pp. 138–143.

  56. S. A. Fahmy, C. -S. Bouganis, P. Y. K. Cheung, and W. Luk, “Efficient Realtime FPGA Implementation of the Trace Transform”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006, pp. 555–560.

  57. S. A. Fahmy, P. Y. K. Cheung, and W. Luk, “Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing”, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 2005, pp. 142–147.

  58. S. A. Fahmy, P. Y. K. Cheung, and W. Luk, “Hardware Acceleration of Hidden Markov Model Decoding for Person Detection”, in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Munich, Germany, March 2005, pp. 8–13.

Peer-Reviewed Journal and Magazine Articles

  1. T. H. Pham, S. A. Fahmy, and I. V. McLoughlin, “An End-to-End Multi-Standard OFDM Transceiver Architecture Using FPGA Partial Reconfiguration”, in IEEE Access, vol. 5, pp. 21002–20015, 2017.

  2. S. Shreejith, P. Mundhenk, A. Ettner, S. A. Fahmy, S. Steinhorst, M. Lukasiewycz, and S. Chakraborty, “VEGa: A High Performance Vehicular Ethernet Gateway on Hybrid FPGA”, in IEEE Transactions on Computers, vol. 66 no. 10, pp. 1790–1803, October 2017.

  3. B. Ronak and S. A. Fahmy, “Multi-pumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs”, in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 36, no. 9, pp. 1471–1482, September 2017.

  4. R. Warrier, S. Shreejith, W. Zhang C. H. Vun, and S. A. Fahmy, “Fracturable DSP Block for Multi-context Reconfigurable Architectures”, in Circuits, Systems, and Signal Processing, vol. 36, no. 7, pp. 3020–2033, July 2017, Springer.

  5. P. Mundhenk, A. Paverd, A. Mrowca, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, and S. Chakraborty, “Security in Automotive Networks: Lightweight Authentication and Authorization”, in ACM Transactions on Design Automation of Electronic Systems, vol. 22, no. 2, pp. 25:1–25:27, March 2017.

  6. M. Asiatici, N. George, K. Vipin, S. A. Fahmy, and P. Ienne, “Virtualized Execution Runtime for FPGA Accelerators in the Cloud”, in IEEE Access, vol. 5, pp. 1900–1910, 2017.

  7. P. Mundhenk, A. Mrowca, S. Steinhorst, M. Lukasiewycz, S. A. Fahmy, S. Chakraborty, “Open Source Model and Simulator for Real-Time Performance Analysis of Automotive Network Security”, in ACM SIGBED Review, vol. 13, no. 3, pp. 8–13, June 2016.

  8. T. H. Pham, S. A. Fahmy, and I. V. McLoughlin, “Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1412–1420, April 2016.

  9. B. Ronak and S. A. Fahmy, “Mapping for Maximum Performance on FPGA DSP Blocks”, in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 35, no. 4, pp. 573–585, April 2016.

  10. T. H. Pham, S. A. Fahmy, and I. V. McLoughlin, “Spectrally Efficient Emission Mask Shaping for OFDM Cognitive Radios” in Digital Signal Processing, vol. 50, pp. 150–161, March 2016, Elsevier.

  11. A. Ambede, S. Shreejith, A. P. Vinod, and S. A. Fahmy, “Design and Realization of Variable Digital Filters for Software Defined Radio Channelizers using Improved Coefficient Decimation Method”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 1, pp. 59–63, January 2016.

  12. S. Shreejith and S. A. Fahmy, “Extensible FlexRay Communication Controller for FPGA-Based Automotive Systems”, in IEEE Transactions on Vehicular Technology, vol. 64, no. 2, pp. 453–465, February 2015.

  13. A. K. Jain, K. D. Pham, J. Cui, S. A. Fahmy, and D. L. Maskell, “Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform”, in Journal of Signal Processing Systems, vol. 77, no. 1–2, pp. 61–76, October 2014, Springer.

  14. K. Vipin and S. A. Fahmy, “ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq”, in IEEE Embedded Systems Letters, vol. 6, no. 3, pp. 41–44, September 2014.

  15. H. Y. Cheah, F. Brosser, S. A. Fahmy, and D. L. Maskell, “The iDEA DSP Block Based Soft Processor for FPGAs”, in ACM Transactions on Reconfigurable Technology and Systems, vol. 7, no. 3, Article 19, August 2014.

  16. T. H. Pham, I. V. McLoughlin, and S. A. Fahmy, “Robust and Efficient OFDM Synchronisation for FPGA-Based Radios”, in Circuits, Systems, and Signal Processing, vol. 33, no. 8, pp. 2475–2493, August 2014, Springer.

  17. T. H. Pham, S. A. Fahmy, and I.V. McLoughlin, “Low-Power Correlation for IEEE 802.16 OFDM Synchronisation on FPGA”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 8, pp. 1549–1553, August 2013.

  18. S. A. Fahmy and A. R. Mohan, “Architecture for Real-Time Nonparametric Probability Density Function Estimation”, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 5, pp. 910–920, May 2013.

  19. S. Shreejith, S. A. Fahmy, and M. Lukasiewycz, “Reconfigurable Computing in Next-Generation Automotive Networks”, in IEEE Embedded Systems Letters, vol. 5, no. 1, pp. 12–15, March 2013.

  20. J. Lotze, S. A. Fahmy, J. Noguera, and L.E. Doyle, “A Model-Based Approach to Cognitive Radio Design”, in IEEE Journal on Selected Areas in Communications (JSAC), vol. 29, no. 2, pp. 455–468, February 2011.

  21. P. D. Sutton, J. Lotze, H. Lahlou, S. A. Fahmy, K.E. Nolan, B. Özgül, T. W. Rondeau, J. Noguera, and L.E. Doyle, “Iris – An Architecture for Cognitive Radio Networking Testbeds”, in IEEE Communications Magazine, vol. 48, no. 9, pp. 114–122, September 2010.

  22. S. A. Fahmy, P. Y. K. Cheung, and W. Luk, “High-Throughput One-Dimensional Median and Weighted Median Filters on FPGA”, in IET Computers and Digital Techniques (IET-CDT), vol. 3, no. 4, pp. 384–394, July 2009.

  23. S. A. Fahmy, C. -S. Bouganis, P. Y. K. Cheung, and W. Luk, “Real-Time Hardware Acceleration of the Trace Transform”, in Journal of Real-Time Image Processing, vol. 2, no. 4, pp. 235–248, December 2007, Springer.

Posters, Reports, and Demonstrations

  1. R. Cooke and S. A. Fahmy, “In-network online data analytics with FPGAs”, PhD Forum Poster in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, September 2017.

  2. A. K. Jain, D. L. Maskell, S. A. Fahmy, “Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays”, presented at 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017), Monterey, CA, February 2017.

  3. M. Asiatici, N. George, K. Vipin, S. A. Fahmy, P. Ienne, “Designing a Virtual Runtime for FPGA Accelerators in the Cloud”, PhD Forum Poster in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, August 2016.

  4. B. Ronak and S. A. Fahmy, “Initiation Interval Aware Resource Sharing for FPGA DSP Blocks”, Poster in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Washington, DC, May 2016.

  5. X. Li, A. K. Jain, D. L. Maskell, S. A. Fahmy, “An Area-Efficient FPGA Overlay Using DSP Block Based Time-Multiplexed Functional Units”, presented at 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016), Monterey, CA, February 2016.

  6. L. Yang, S. T. Gurumani, S. A. Fahmy, D. Chen, K. Rupnow, “Automated Verification Code Generation in HLS Using Software Execution Traces”, Poster in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, CA, February 2016, pp. 278.

  7. S. A. Fahmy and K. Vipin, “A Case for FPGA Accelerators in the Cloud”, Poster at ACM Symposium on Cloud Computing (SoCC), Seattle, WA, November 2014.

  8. T. H. Pham, S. A. Fahmy, and I. V. McLoughlin, “Efficient Multi-Standard Cognitive Radios on FPGAs”, PhD Forum Poster in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, September 2014.

  9. K. S. H. Ong, S. A. Fahmy, and K.-V. Ling, “A Scalable and Compact Systolic Architecture for Linear Solvers”, Poster in Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Zurich, Switzerland, June 2014, pp. 186–187.

  10. B. Ronak and S. A. Fahmy, “Experiments in Mapping Expressions to DSP Blocks”, Poster in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014, pp. 101.

  11. S. Shreejith and S. A. Fahmy, “Enhancing Communication On Automotive Networks Using Data Layer Extensions”, Demonstration Paper in Proceedings of the International Conference on Field Programmable Technology (FPT), Kyoto, Japan, December 2013, pp. 470–473.

  12. K. Vipin and S. A. Fahmy, “An Approach to a Fully Automated Partial Reconfiguration Design Flow”, Poster in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Seattle, WA, April 2013, pp. 231.

  13. K. Vipin and S. A. Fahmy, [“Enabling High Level Design of Adaptive Systems with Partial Reconfiguration”][fpt2011-vipin-phd], PhD Forum Paper in Proceedings of the International Conference on Field Programmable Technology (FPT), New Delhi, India, December 2011.

  14. K. Vipin and S. A. Fahmy, “A Threat Based Connect6 Implementation on FPGA”, Design Competition Paper in Proceedings of the International Conference on Field Programmable Technology (FPT), New Delhi, India, December 2011.

  15. J. Lotze, S. A. Fahmy, J. Noguera, and L. Doyle, “An FPGA-Based Autonomous Adaptive Radio”, Demonstration Poster, ACM SIGCOMM, Barcelona, Spain, August 2009.

  16. J. Lotze, B. Ozgül, S. A. Fahmy, J. Noguera, L. Doyle, and R. Esser, “Spectrum Sensing to Achieve Frequency Rendezvous using Xilinx FPGAs”, demonstrated at IEEE Symposia on New Frontiers in Dynamic Spectrum Access Networks (DySPAN), Chicago, Illinois, October 2008.

  17. J. Lotze, S. A. Fahmy, J. Noguera, L. Doyle, and R. Esser, “High-level Cognitive Radio Design Using Xilinx FPGAs”, demonstrated at Collaborative International Software Defined Radio Workshop (CISDR), Maynooth, Ireland, May 2008.

  18. S. A. Fahmy, “Investigating Trace Transform Architectures for Face Authentication”, PhD Forum Poster in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006, pp. 929–930.

Book Chapter

  • C. -S. Bouganis, S. A. Fahmy, and P. Y. K. Cheung, “From Algorithms to Hardware Implementation” in Next Generation Artifical Vision Systems: Reverse Engineering the Human Visual System, A. Bharath and M. Petrou Eds., Artech House, 2008, pp. 367–393.

PhD Thesis